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INTEGRATED CIRCUITS
DATA SHEET
TDA8761 9-bit analog-to-digital converter for digital video
Preliminary specification File under Integrated Circuits, IC02 1995 Mar 20
Philips Semiconductors
Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for digital video
FEATURES * 9-bit resolution * Sampling rate up to 30 MHz * DC sampling allowed * One clock cycle conversion only * High signal-to-noise ratio over a large analog input frequency range (8.5 effective bits at 10 MHz full-scale input at fclk = 30 MHz) * No missing codes guaranteed * In range (IR) 3-state TTL output * TTL compatible digital inputs and outputs * Low-level AC clock input signal allowed * External reference voltage regulator * Power dissipation only 360 mW (typical) * Low analog input capacitance, no buffer amplifier required * No sample-and-hold circuit required. QUICK REFERENCE DATA SYMBOL VCCA VCCD VCCO ICCA ICCD ICCO AINL ADNL fclk(max) Ptot Note 1. fi = 11 MHz and fclk = 30 MHz; fi = 8 MHz and fclk = 20 MHz. ORDERING INFORMATION TYPE NUMBER TDA8761M PACKAGE NAME SSOP28 DESCRIPTION plastic shrink small outline package; 28 leads; body width 5.3 mm PARAMETER analog supply voltage digital supply voltage output stages supply voltage analog supply current digital supply current output stages supply current AC integral non-linearity AC differential non-linearity maximum clock frequency total power dissipation note 1; full scale input sine wave note 1; 50% full scale input sine wave note 1; full scale input sine wave note 1; 50% full scale input sine wave CONDITIONS MIN. 4.75 4.75 4.4 - - - - - - - 30 - TYP. 5.0 5.0 5.0 30 22 22 0.75 0.5 0.5 0.3 - 360 APPLICATIONS Analog-to-digital conversion for: * Video data digitizing * Digital Video Broadcasting (DVB) * Cable TV. GENERAL DESCRIPTION
TDA8761
The TDA8761 is a 9-bit analog-to-digital converter (ADC) for professional video and digital video set box applications. It converts the analog input signal into 9-bit binary-coded digital words at a maximum sampling rate of 30 MHz. Its linearity performance ensures the required conversion accuracy in case of 256QAM demodulator concept and for all symbol frequencies. All digital inputs and outputs are TTL compatible, although a low-level sine wave clock input signal is allowed.
MAX. 5.25 5.25 5.25 tbf tbf tbf tbf tbf tbf tbf - tbf
UNIT V V V mA mA mA LSB LSB LSB LSB MHz mW
VERSION SOT341-1
1995 Mar 20
2
Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for digital video
BLOCK DIAGRAM
TDA8761
handbook, full pagewidth
V CCA 3
CLK 1
VCCD 11
CE 10
CLOCK DRIVER VRT
2
TC
TDA8761
9
25 D8 24 D7 23 D6 22 D5 analog voltage input VI 8 ANALOG -TO - DIGITAL CONVERTER LATCHES TTL OUTPUTS 21 D4 20 D3 19 D2 18 D1 17 D0 LSB data outputs MSB
VRM
7
VRB 6
13
VCCO1
28 VCCO2 IN RANGE LATCH TTL OUTPUT 26 IR output
4 AGND1
5 AGND2
12 DGND
14 OGND1
27 OGND2
MGC355
analog grounds
digital ground
output grounds
Fig.1 Block diagram.
1995 Mar 20
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Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for digital video
PINNING SYMBOL CLK TC VCCA AGND1 AGND2 VRB VRM VI VRT CE VCCD DGND VCCO1 OGND1 n.c. n.c. D0 D1 D2 D3 D4 D5 D6 D7 D8 IR OGND2 VCCO2 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 clock input two's complement input (active LOW) analog supply voltage (+5 V) analog ground 1 analog ground 2 reference voltage BOTTOM input reference voltage MIDDLE analog input voltage reference voltage TOP input chip enable input (TTL level input, active LOW) digital supply voltage (+5 V) digital ground supply voltage for output stages 1 (+5 V) output ground 1 not connected not connected data output; bit 0 (LSB) data output; bit 1 data output; bit 2 data output; bit 3 data output; bit 4 data output; bit 5 data output; bit 6 data output; bit 7 data output; bit 8 (MSB) in range data output output ground 2 supply voltage for output stages 2 (+5 V) Fig.2 Pin configuration.
handbook, halfpage
TDA8761
DESCRIPTION
CLK TC VCCA AGND1 AGND2 VRB VRM VI VRT
1 2 3 4 5 6 7
28 VCCO2 27 OGND2 26 IR 25 D8 24 D7 23 D6 22 D5
TDA8761
8 9 21 D4 20 D3 19 D2 18 D1 17 D0 16 n.c. 15 n.c.
MGC356
CE 10 VCCD 11 DGND 12 V CCO1 13 OGND1 14
1995 Mar 20
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Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for digital video
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCCA VCCD VCCO VCC PARAMETER analog supply voltage digital supply voltage output stages supply voltage supply voltage differences between VCCA and VCCD VCCO and VCCD VCCA and VCCO VI Vi(p-p) IO Tstg Tamb Tj Note input voltage AC input voltage for switching (peak-to-peak value) output current storage temperature operating ambient temperature junction temperature referenced to AGND referenced to DGND -1.0 -1.0 -1.0 -0.3 - - -55 0 - +1.0 +1.0 +1.0 +7.0 VCCD 10 +150 +70 +150 CONDITIONS note 1 note 1 note 1 MIN. -0.3 -0.3 -0.3
TDA8761
MAX. +7.0 +7.0 +7.0 V V V V V V V V
UNIT
mA C C C
1. The supply voltages VCCA, VCCD and VCCO may have any value between -0.3 V and +7.0 V provided the difference between VCCA, VCCD and VCCO is between -1 and +1 V. HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE 110 UNIT K/W
1995 Mar 20
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Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for digital video
TDA8761
CHARACTERISTICS VCCA = V3 to V4 and V5 = 4.75 to 5.25 V; VCCD = V11 to V12 = 4.75 to 5.25 V; VCCO = V13 and V28 to V14 and V27 = 4.4 to 5.25 V; AGND and DGND shorted together; Tamb = 0 to +70 C; typical values measured at VCCA = VCCD = VCCO = 5 V; Vi(p-p) = 1.5 V; CL = 15 pF and Tamb = 25 C; unless otherwise specified. SYMBOL Supply VCCA VCCD VCCO VCC analog supply voltage digital supply voltage output stages supply voltage supply voltage differences between VCCA and VCCD VCCA and VCCO VCCD and VCCO ICCA ICCD ICCO Inputs CLOCK INPUT CLK (REFERENCED TO DGND); note 1 VIL VIH IIL IIH ZI CI VIL VIH IIL IIH IIL IIH ZI CI LOW level input voltage HIGH level input voltage LOW level input current HIGH level input current input impedance input capacitance Vclk = 0.4 V Vclk = 2.7 V fclk = 30 MHz fclk = 30 MHz 0 2.0 -1 - - - 0 2.0 VIL = 0.4 V VIH = 2.7 V VI = 1.3 V VI = 3.8 V fi = 10 MHz fi = 10 MHz -400 - - - - - - - 0 - 2 2 - - - - 0 70 5 8 0.8 VCCD +1 20 - - 0.8 VCCD - 20 - - - - V V A A k pF analog supply current digital supply current output stages supply current -0.25 -0.4 -0.4 - - - - - - 30 22 22 +0.25 +0.4 +0.4 tbf tbf tbf V V V mA mA mA 4.75 4.75 4.4 5.0 5.0 5.0 5.25 5.25 5.25 V V V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
INPUT CE (REFERENCED TO DGND); see Table 2 LOW level input voltage HIGH level input voltage LOW level input current HIGH level input current V V A A A A k pF
VI (ANALOG INPUT VOLTAGE REFERENCED TO AGND) LOW level input current HIGH level input current input impedance input capacitance
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Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for digital video
SYMBOL PARAMETER CONDITIONS MIN. TYP. - 3.0 - - - - - - 2.5
TDA8761
MAX.
UNIT
Reference voltages for the resistor ladder; see Table 1 VRB VRT Vdiff Iref RLAD TCRLAD VosB VosT Vi(p-p) Outputs DIGITAL OUTPUTS D8 TO D0 AND IR (REFERENCED TO OGND) VOL VOH LOW level output voltage HIGH level output voltage IO = 1 mA IO = 0 mA IO = -0.4 mA IO = -1 mA IOZ output current in 3-state mode 0.4 V < VO < VCCO Switching characteristics CLOCK INPUT CLK; see Fig.3; note 1 fclk(max) tCPH tCPL maximum clock frequency clock pulse width HIGH clock pulse width LOW 30 10 10 - - - - - - MHz ns ns 0 2.7 2.7 2.4 -20 - - - - - 0.4 VCCO - 0.5 VCCO - 1.3 VCCO - 1.4 +20 V V V V A reference voltage BOTTOM reference voltage TOP differential reference voltage VRT - VRB reference current resistor ladder temperature coefficient of the resistor ladder offset voltage BOTTOM offset voltage TOP analog input voltage (peak-to-peak value) note 2 note 2 note 3 1.2 - 1.8 - - - - - - 1.3 1.3 3.3 2.0 30 85 1.86 158 250 250 1.5 V V mA ppm m/K mV mV V VCCA - 0.8 V V
Analog signal processing LINEARITY AINL AC integral non-linearity note 5; full scale input sine wave note 5; 50% full scale input sine wave ADNL AC differential non-linearity note 5; full scale input sine wave note 5; 50% full scale input sine wave OFER GER offset error gain error (from device to device) - - - - 0.75 0.5 0.5 0.3 1 0.1 tbf tbf tbf tbf - - LSB LSB LSB LSB LSB %
- middle code; VRB = 1.3 V; VRT = 3.3 V VRB = 1.3 V; VRT = 3.3 V; note 4 -
1995 Mar 20
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Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for digital video
SYMBOL PARAMETER CONDITIONS MIN. - - - TYP. - - -
TDA8761
MAX.
UNIT
BANDWIDTH (fclk = 30 MHz) B analog bandwidth full-scale sine wave; note 6 75% full-scale sine wave; note 6 small signal at mid-scale; VI = 10 LSB at code 256; note 6 tSTLH tSTHL analog input settling time LOW-to-HIGH analog input settling time HIGH-to-LOW full-scale square wave; Fig.5; note 7 full-scale square wave; Fig.5; note 7 40 55 700 MHz MHz MHz
- -
2.0 2.5
tbf tbf
ns ns
HARMONICS (fclk = 30 MHZ) THD total harmonic distortion fi = 10 MHz without harmonics; fclk = 30 MHz; fi = 10 MHz fclk = 30 MHz; fi = 10 MHz fclk = 30 MHz fclk = 30 MHz; fi = 10 MHz; VI = 16 LSB at code 256 - 53 -64 55 - - dB SIGNAL-TO-NOISE RATIO; see Fig.7; note 8 S/N signal-to-noise ratio (full scale) dB
EFFECTIVE BITS; see Fig 6; note 8 EB effective bits - 8.5 - bits
TWO-TONE; note 9 TTIR two-tone intermodulation rejection - - -64 10-13 - - dB
BIT ERROR RATE BER bit error rate times/ sample
DIFFERENTIAL GAIN; note 10 Gdiff differential gain fclk = 30 MHz; PAL modulated ramp - tbf - %
DIFFERENTIAL PHASE; note 10 diff differential phase fclk = 30 MHz; PAL modulated ramp - tbf - deg
Timing (fclk = 30 MHz; CL = 15 pF); see Fig.3; note 11 tds th td CL sampling delay time output hold time output delay time digital output load - 5 - - - - 10 15 2 - 14 40 ns ns ns pF
1995 Mar 20
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Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for digital video
SYMBOL PARAMETER CONDITIONS MIN. - - - - TYP.
TDA8761
MAX.
UNIT
3-state output delay times; see Fig.4 tdZH tdZL tdHZ tdLZ Notes 1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 0.5 ns. 2. Analog input voltages producing code 0 up to and including code 511: a) VosB (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and the reference voltage BOTTOM (VRB) at Tamb = 25 C. b) VosT (voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which produces data outputs equal to code 511 at Tamb = 25 C. ( V RT - V RB ) x 8 3. Analog input voltage range can be derived from VRT - VRB difference. It is ------------------------------------------9 4. ( V 511 - V 0 ) - 1.5 V GER = --------------------------------------------------- x 100 1.5 V enable HIGH enable LOW disable HIGH disable LOW tbf tbf tbf tbf tbf tbf tbf tbf ns ns ns ns
5. fi = 11 MHz and fclk = 30 MHz; fi = 8 MHz and fclk = 20 MHz. 6. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No glitches greater than 2 LSBs, neither any significant attenuation are observed in the reconstructed signal. 7. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square-wave signal) in order to sample the signal and obtain correct output data. 8. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency (NYQUIST frequency). Conversion to signal-to-noise ratio: S/N = EB x 6.02 + 1.76 dB. 9. Intermodulation measured relative to either tone with analog input frequencies of 10.0 MHz and 10.10 MHz. The two input signals have the same amplitude and the total amplitude of both signals provides full scale to the converter. 10. Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a digital-to-analog converter. 11. Output data acquisition: the output data is available after the maximum delay time of td.
1995 Mar 20
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Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for digital video
Table 1 STEP U/F 0 1 . . 510 511 O/F Table 2
TDA8761
Output coding and input voltage (typical values; referenced to AGND, VRB = 1.3 V, VRT = 3.3 V) BINARY OUTPUT BITS VI(p-p) <1.55 1.55 . . . . 3.05 >3.05 IR D8 0 1 1 . . 1 1 0 0 0 0 . . 1 1 1 D7 0 0 0 . . 1 1 1 D6 0 0 0 . . 1 1 1 D5 0 0 0 . . 1 1 1 D4 0 0 0 . . 1 1 1 D3 0 0 0 . . 1 1 1 D2 0 0 0 . . 1 1 1 D1 0 0 0 . . 1 1 1 D0 0 0 1 . . 1 1 1 D8 0 0 0 . . 1 1 1 D7 0 0 0 . . 1 1 1 D6 0 0 0 . . 1 1 1 D5 0 0 0 . . 1 1 1 D4 0 0 0 . . 1 1 1 D3 0 0 0 . . 1 1 1 D2 0 0 0 . . 1 1 1 D1 0 0 0 . . 1 1 1 D0 0 0 1 . . 0 1 1 TWO'S COMPLEMENT OUTPUT BITS
Mode selection CE 1 0 0 D8 TO D0 high impedance active; two's complement active; binary high impedance active active IR
TC X 0 1
handbook, full pagewidth
t CPL t CPH CLK 1.4 V
sample N
sample N + 1
sample N + 2
Vl
t ds DATA D0 to D8 DATA N-2 DATA N-1 td
th 2.4 V DATA N DATA N+1
MGC357
1.4 V 0.4 V
Fig.3 Timing diagram.
1995 Mar 20
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Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for digital video
TDA8761
handbook, full pagewidth
V CCD CE 50 %
t dHZ HIGH 90 % output data t dLZ HIGH output data LOW 10 % 50 % t dZL LOW
t dZH
50 %
TEST V CCD 3.3 k TDA8761 15 pF CE S1 t dLZ t dZL t dHZ t dZH
S1 VCCD VCCD GND GND
MGC358
f CE = 100 kHz.
Fig.4 Timing diagram and test conditions of 3-state output delay time.
1995 Mar 20
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Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for digital video
TDA8761
t STLH
handbook, full pagewidth
t STHL
code 511 VI code 0 2 ns 2 ns 50 % 50 %
CLK
50 %
50 %
MGC359
0.5 ns
0.5 ns
Fig.5 Analog input settling-time diagram.
0
handbook, full pagewidth
MGC360
amplitude (dB) 20
40
60
80
100
120 0 1.88 3.75 5.63 7.50 9.37 11.3 13.1 f (MHz) 15.0
Effective bits: 8.58; THD = -61.80 dB. Harmonic levels (dB): 2nd = -64.77; 3rd = -79.30; 4th = -71.90; 5th = -66.12; 6th = -82.29.
Fig.6 Fast Fourier Transform (fclk = 30 MHz; fi = 10 MHz). 1995 Mar 20 12
Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for digital video
INTERNAL PIN CONFIGURATIONS
TDA8761
handbook, halfpage
VCCO2
handbook, halfpage
VCCO1
V CCA
D8 to D0 O/UF
VI
OGND1
MGC361
AGND
MGC040
Fig.7 TTL data and in-range outputs.
Fig.8 Analog inputs.
ndbook, halfpage
VCCO1 VCCA
handbook, halfpage
VRT CE (TC) VRM R LAD VRB
AGND
MEA050
OGND2
MGC041
Fig.9 CE (TC) 3-state input.
Fig.10 VRB, VRM and VRT. 13
1995 Mar 20
Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for digital video
TDA8761
handbook, full pagewidth
VCCD
CLK
V ref (1.3 V)
DGND
MGC042
Fig.11 CLK input.
1995 Mar 20
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Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for digital video
APPLICATION INFORMATION
TDA8761
handbook, halfpage
CLK
1
28
V CCO2
TC VCCA
2
27
OGND2
3
26
IR
AGND1
4
25
D8
AGND2
(1)
5
24
D7
V RB 100 nF AGND VI 100 nF
(1) (1)
6
23 D6 D5
V RM
7 TDA8761 8
22
21
D4
AGND 100 nF
V RT
9
20
D3
CE AGND V CCD
10
19
D2
11
18
D1
DGND V CCO1
12
17
D0
(2)
13
16
n.c.
(2)
OGND1
14
15
MGC362
n.c.
The analog and digital supplies should be separated and decoupled. The external voltage generator must be built such that a good supply voltage ripple rejection is achieved with respect to the LSB value. Eventually, the reference ladder voltages can be derived from a well regulated VCCA supply through a resistor bridge and a decoupled capacitor. For applications where the input signal must remain well centred around middle scale, VRM must be decoupled and connected to analog input signal (pin 8) through a resistor. The values must be defined in accordance with the input signal frequency in order to avoid direct coupling into the ADC ladder (e.g. R = 5 k and C = 100 nF). (1) VRB, VRM and VRT are decoupled to AGND. (2) Pins 15 and 16 should be connected to DGND in order to prevent noise influence.
Fig.12 Application diagram.
1995 Mar 20
15
Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for digital video
PACKAGE OUTLINE SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm
TDA8761
SOT341-1
D
E
A X
c y HE vMA
Z 28 15
Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 14 wM detail X A
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT341-1 REFERENCES IEC JEDEC MO-150AH EIAJ EUROPEAN PROJECTION A max. 2.0 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 10.4 10.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.1 0.7 8 0o
o
ISSUE DATE 93-09-08 95-02-04
1995 Mar 20
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Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for digital video
SOLDERING Plastic small outline packages BY WAVE During placement and before soldering, the component must be fixed with a droplet of adhesive. After curing the adhesive, the component can be soldered. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 C within 6 s. Typical dwell time is 4 s at 250 C. A modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. Using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. BY SOLDER PASTE REFLOW Reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA8761
Several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. Dwell times vary between 50 and 300 s according to method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 min at 45 C. REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
IRON OR PULSE-HEATED SOLDER TOOL)
Fix the component by first soldering two, diagonally opposite, end pins. Apply the heating tool to the flat part of the pin only. Contact time must be limited to 10 s at up to 300 C. When using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 C. (Pulse-heated soldering is not recommended for SO packages.) For pulse-heated solder tool (resistance) soldering of VSO packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1995 Mar 20
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Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for digital video
NOTES
TDA8761
1995 Mar 20
18
Philips Semiconductors
Preliminary specification
9-bit analog-to-digital converter for digital video
NOTES
TDA8761
1995 Mar 20
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Philips Semiconductors - a worldwide company
Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. (02)805 4455, Fax. (02)805 4466 Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Tel. (31)40 783 749, Fax. (31)40 788 399 Brazil: Rua do Rocio 220 - 5th floor, Suite 51, CEP: 04552-903-SAO PAULO-SP, Brazil. P.O. Box 7383 (01064-970), Tel. (011)821-2333, Fax. (011)829-1849 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS: Tel. (800) 234-7381, Fax. (708) 296-8556 Chile: Av. Santa Maria 0760, SANTIAGO, Tel. (02)773 816, Fax. (02)777 6730 Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17, 77621 BOGOTA, Tel. (571)249 7624/(571)217 4609, Fax. (571)217 4549 Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. (032)88 2636, Fax. (031)57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. (9)0-50261, Fax. (9)0-520971 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. (01)4099 6161, Fax. (01)4099 6427 Germany: P.O. Box 10 63 23, 20043 HAMBURG, Tel. (040)3296-0, Fax. (040)3296 213. Greece: No. 15, 25th March Street, GR 17778 TAVROS, Tel. (01)4894 339/4894 911, Fax. (01)4814 240 Hong Kong: PHILIPS HONG KONG Ltd., 15/F Philips Ind. Bldg., 24-28 Kung Yip St., KWAI CHUNG, N.T., Tel. (852)424 5121, Fax. (852)480 6960/480 6009 India: Philips INDIA Ltd, Shivsagar Estate, A Block , Dr. Annie Besant Rd. Worli, Bombay 400 018 Tel. (022)4938 541, Fax. (022)4938 722 Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4, P.O. Box 4252, JAKARTA 12950, Tel. (021)5201 122, Fax. (021)5205 189 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. (01)7640 000, Fax. (01)7640 200 Italy: PHILIPS SEMICONDUCTORS S.r.l., Piazza IV Novembre 3, 20124 MILANO, Tel. (0039)2 6752 2531, Fax. (0039)2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, TOKYO 108, Tel. (03)3740 5028, Fax. (03)3740 0580 Korea: (Republic of) Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. (02)794-5011, Fax. (02)798-8022 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556 Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB Tel. (040)783749, Fax. (040)788399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. (09)849-4160, Fax. (09)849-7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. (022)74 8000, Fax. (022)74 8341 Pakistan: Philips Electrical Industries of Pakistan Ltd., Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton, KARACHI 75600, Tel. (021)587 4641-49, Fax. (021)577035/5874546 Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc, 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474 Portugal: PHILIPS PORTUGUESA, S.A., Rua dr. Antonio Loureiro Borges 5, Arquiparque - Miraflores, Apartado 300, 2795 LINDA-A-VELHA, Tel. (01)4163160/4163333, Fax. (01)4163174/4163366 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. (65)350 2000, Fax. (65)251 6500 South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430, Johannesburg 2000, Tel. (011)470-5911, Fax. (011)470-5494. Spain: Balmes 22, 08007 BARCELONA, Tel. (03)301 6312, Fax. (03)301 42 43 Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM, Tel. (0)8-632 2000, Fax. (0)8-632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. (01)488 2211, Fax. (01)481 77 30 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978, TAIPEI 100, Tel. (02)388 7666, Fax. (02)382 4382 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, Bangkok 10260, THAILAND, Tel. (662)398-0141, Fax. (662)398-3319 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. (0 212)279 27 70, Fax. (0212)282 67 07 United Kingdom: Philips Semiconductors LTD., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. (0181)730-5000, Fax. (0181)754-8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556 Uruguay: Coronel Mora 433, MONTEVIDEO, Tel. (02)70-4044, Fax. (02)92 0601
Internet: http://www.semiconductors.philips.com/ps/ For all other countries apply to: Philips Semiconductors, International Marketing and Sales, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Telex 35000 phtcnl, Fax. +31-40-724825 SCD39 (c) Philips Electronics N.V. 1995
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
533061/1500/01/pp20 Document order number: Date of release: 1995 Mar 20 9397 750 00112
Philips Semiconductors

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